Altera Cyclone V

Product features:

• All hardware included
• Available for Sercos III master and slave controllers (SERCON100M/S)

The IP core is available for Sercos III master and slave controllers (SERCON100M/S). It includes all hardware functions, such as timing, synchronization and processing of cyclic and non-cyclic data on the basis of two integrated Ethernet MACs.

Sercos III master and slave devices can be implemented as a single chip solution using either Cyclone V FPGAs or Cyclone V SoCs, which integrate an ARM® dual-core Cortex™-A9 processor. 

Detailed documentation on the IP core, reference designs and example Ethernet interface diagrams are available from Sercos International. Technical support and customer-specific design services are provided by Cannon-Automata, Ried/Germany and Caronno, Pertusella/Italy (http://www.cannon-automata.com).